The present invention relates to a semiconductor memory device that stores desired data and also permits data write and read operation at high speed.
A dynamic random access memory (DRAM) device, for example, among various types of semiconductor memory devices, has been frequently used as a semiconductor memory device capable of recording and holding a large capacity of data.
In recent years, with the tendency of a finer design rule in the semiconductor process, the DRAM cell structure generally composed of one transistor and one capacitor has been complicated, and thus the process cost has become increasingly high. For this reason, in a so-called system LSI in which both a DRAM circuit and an arithmetic-logic circuit are fabricated, there is often used a DRAM cell having a simple planer structure in which a MOS transistor is used in place of the capacitor for reduction of the process cost.
FIG. 9 shows an exemplary configuration of a DRAM cell disclosed in U.S. Pat. No. 5,600,598, in which a MOS transistor is used as a capacitor.
As shown in FIG. 9, the conventional DRAM cell includes an access transistor 101 that is a first MOS transistor having its gate and drain connected to a word line WL and a bit line BL, respectively, and a charge storage transistor 102 that is a second MOS transistor for storing charge in its channel. The source and drain of the charge storage transistor 102 are connected to the source of the access transistor 101, and the gate thereof is connected to a cell plate.
In the DRAM cell having the configuration described above, during write operation, for example, the word line WL is activated, and when the voltage value of the bit line BL is in a high level at this time, “1” is written in the channel of the charge storage transistor 102. Contrarily, when the voltage value of the bit line BL is in a low level, “0” is written in the channel.
During read operation, by activation of the word line WL, charge stored in the channel of the charge storage transistor 102 is transferred to the precharged bit line BL, and the potential of the bit line BL is amplified with a sense amplifier connected to the bit line BL, so that data in the selected DRAM cell is read.
In recent years, further enhancement in performance has been demanded for LSI systems, and in this relation, it is requested to enhance the performance of semiconductor memory devices (memory blocks). DRAM cells are advantageously used when a large-capacity memory device is required because each DRAM cell is composed of a smaller number of elements compared with a SRAM cell. In DRAM cells, however, information (charge) stored in a capacitor disappears with time. Therefore, to hold the recorded data, it is necessary to execute so-called refresh operation, in which the data is read and rewritten repeatedly, before the data disappears. This requirement that refresh operation must be executed constantly during the running of the device is a factor of impairing usability of DRAM devices.
The number of times of the refresh operation did not present a big problem because a sufficient amount of charge was stored in conventional capacitors. However, with the recent tendency of finer memory cells and use of MOS transistors as capacitors, it has become increasingly difficult to secure a sufficient capacitance value for capacitors. As a result, more frequent refresh operation is required, and this disadvantageously impairs the operation of the system.